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The Non-volatile
Systems Laboratory is collecting data on a wide range of flash
memory
devices to provide context and grounding for academic and industrial
research into new applications for flash and other non-volatile memory
technologies. The results of our initial study (acquired with our
custom-built flash characterization system pictured at right) are available below.
Our detailed data includes operation latency, power and energy
consumption, bandwidth, disturbs, wear-induced error rates, and other
performance and failure mode characteristics.
We are actively seeking industrial partners for this
project who can assist us in identifying flash parameters critical to
particular applications and in acquiring small quantities of
cutting-edge flash devices.
For more information, please contact Dr. Steven Swanson (swanson@cs.ucsd.edu).
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Program
speed for pages in an MLC block show dramatic and predictable
variations in latency.
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Power
consumption across chips and operations varies widely.
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Wear-induced
error rates vary widely between devices. The NVSL and CMRR are working to design new tyes
of ECC to ensure reliability.
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Publications
Grupp, L., Caulfield, A.M., Coburn, J., Yaakobi, E., Swanson, S.,
Siegel, P.,
"Characterizing Flash Memory: Anomalies, Observations, and
Applications" To appear in MICRO'09. (pdf) (Flash memory summit slides)
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